Effect of PN passivation on MOSFETs performance in 28 nm FD-SOI
(2026) Solid-State Electronics — Vol. 231, p. 109293 (2026)
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- Abstract
- This work investigates, for the first time, how the PN passivation introduced in the fully depleted silicon-on-insulator (FD-SOI) substrate below the buried oxide (BOX) to improve substrate performance for RF applications in 28 nm FD-SOI technology affects active MOSFET parameters. DC performance and low-frequency noise (LFN) of MOSFETs are studied for different substrate resistivities and implant parameters. It is demonstrated that PN passivation impacts the device performance via modification of the back-gate realization.
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Vanbrabant, M., Rack, M., Cathelin, A., Raskin, J.-P., & Kilchytska, V. (2026). Effect of PN passivation on MOSFETs performance in 28 nm FD-SOI. Solid-State Electronics, 231, 109293. https://doi.org/10.1016/j.sse.2025.109293 (Original work published 2026)