Demonstration of Trap Recovery by In-Situ Annealing in 28nm FD-SOI MOSFETs at Cryogenic Temperatures
(2026) Solid-State Electronics — (2026)
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- Abstract
- This work presents the first demonstration of the impact of active in-situ electro-thermal annealing at 4 K on the low frequency noise characteristics of N-type MOS transistor with thin high-k gate oxide from 28 nm Fully Depleted Silicon-on-Insulator (FD-SOI) process. Efficiency of local electro-thermal annealing inducing more than 475 K temperature rise is demonstrated on the device which features random telegraph noise behaviour at a given current level at 4 K, while presenting "typical" 1/f noise behaviour at room temperature. Experimental results reveal random telegraph noise mitigation both in temporal and spectral domains thanks to the traps healing by in-situ annealing at 4 K, with 58 % noise power reduction, without impacting performance at both 4 K and 295 K.
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Citations
Dieuzeide, V. (2026). Demonstration of Trap Recovery by In-Situ Annealing in 28nm FD-SOI MOSFETs at Cryogenic Temperatures. Solid-State Electronics. Submitted. https://hdl.handle.net/2078.5/280579 (Original work published 2026)