Single- versus Double-layer Spiral Inductor on High-Resistivity Trap-Rich Silicon Substrate
(2025) 2025 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP) — Location: Split, Croatia (1.June.2025)
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Single-_versus_Double-layer_Spiral_Inductor_on_High-Resistivity_Trap-Rich_Silicon_Substrate.pdf
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- Abstract
- On-chip spiral inductors are indispensable components in modern integrated circuits (ICs), enabling critical functions across wireless communication, power management, and emerging technologies. This paper presents a comparative analysis of single- and double-layer square spiral inductors in terms of self-inductance, quality factor and resonant frequency, both fabricated on a high-resistivity trap-rich silicon substrate to minimize substrate losses and improve electrical performance. Electromagnetic simulations using ADS software, together with experimental measurements, show that the double-layer inductor achieves a 34.6% increase in self-inductance compared to its single-layer counterpart. However, the single-layer design outperforms the other in terms of quality factor (29.43% decrease) and resonant frequency (62.9% decrease) due to lower resistance and parasitic capacitance in its structure. By balancing the performance trade-offs for specific applications, using calibrated ADS simulations, these results help in selecting the optimal inductor design.
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Citations
Gabbouj, R., Zeidi, N., Flandre, D., & Tounsi, F. (2025). Single- versus Double-layer Spiral Inductor on High-Resistivity Trap-Rich Silicon Substrate. 2025 Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP), 1-6. https://doi.org/10.1109/DTIP66728.2025.11099177 (Original work published 2025)