On Noise-Induced Transient Bit Flips in Subthreshold SRAM
(2023) 9th EUROSOI-ULIS — Location: Tarragona, Spain (10.May.2023)
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- Abstract
- We propose a rigorous SPICE simulation framework, compatible with industrial process design kits, to observe transient bit flips in CMOS SRAM due to the intrinsic transistor noise. The methodology is illustrated in 28 nm FD-SOI technology. We study the combined effects of the random telegraph noise, flicker and thermal noise sources, for the first time to our knowledge. The extracted mean times to failure are compared to those reported in the literature in extreme voltage, temperature and variability conditions.
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Citations
Van Brandt, L., Silveira, F., Delvenne, J.-C., & Flandre, D. (2023). On Noise-Induced Transient Bit Flips in Subthreshold SRAM. 9th EUROSOI-ULIS, Tarragona, Spain. https://hdl.handle.net/2078.5/255200