A 2.24-pJ/bit 2.5-Gb/s UWB receiver in 28-nm FDSOI CMOS for low-energy chip-to-chip communications
(2020) A E Ue: International Journal of Electronics and Communication — Vol. 114, n° 152996, p. 8 (2020)
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- Abstract
- Chip-to-chip communications in high-performance applications such as server racks rely on wireline serial links. In this paper, we present a compact ultra-wideband receiver front-end in 28-nm FDSOI CMOS technology as a wireless interconnect alternative for low-energy and broadcast communications. It is based on binary pulse position modulation without guard interval using two periods of a 10-GHz carrier to reach 2.5-Gb/s datarate over distances >20 cm. The proposed receiver occupies 0.3 mm2 (including decoupling capacitors) and consumes only 5.6 mW which results in an energy of 2.24 pJ/bit.
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Citations
Gimeno Gasca, C., Flandre, D., Schramme, M., Frenkel, C., & Bol, D. (2020). A 2.24-pJ/bit 2.5-Gb/s UWB receiver in 28-nm FDSOI CMOS for low-energy chip-to-chip communications. A E Ue: International Journal of Electronics and Communication, 114(152996), 8. https://doi.org/10.1016/j.aeue.2019.152996 (Original work published 2020)