Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs

Martins d’Oliveira, Ligia;Kilchytska, Valeriya;Planes, Nicolas;Flandre, Denis;de Souza, Michelly
(2019) IEEE S3S Conference — Location: San Jose (USA) (October.2019)

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Authors
  • Martins d’Oliveira, LigiaDepartment of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil
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  • Kilchytska, ValeriyaUCLouvain
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  • Planes, NicolasR&D Process Integration, STMicroelectronics, Crolles, France
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  • Flandre, Denisorcid-logoUCLouvain
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  • de Souza, MichellyDepartment of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil
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Abstract
This paper presents an experimental analysis of the analog characteristics of self-cascode structures composed by 28 nm technological node ultra-thin body and BOX fully-depleted silicon-on-insulator planar MOSFETs, focusing on the subthreshold operation regime. Apart from the increased gain promoted by the reduction of front gate voltage, there is further improvement when the back-gate bias is used to reduce the threshold voltage of transistor close to the drain of the composite device, making this structure a promising option for low-power low-voltage (LPLV) analog applications.
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Martins d’Oliveira, L., Kilchytska, V., Planes, N., Flandre, D., & de Souza, M. (2019). Subthreshold Operation of Self-Cascode Structure Using UTBB FD SOI Planar MOSFETs. IEEE S3S Conference, San Jose (USA). https://hdl.handle.net/2078.5/228447