A Transient Noise Analysis of Secured Dual-rail based Logic Style

Nawaz, Kashif;Levi, Itamar;Standaert, François-Xavier;Flandre, Denis
(2018) 2nd New Generation of Circuits & Systems Conference (NGCAS 2018) — Location: Valetta (Malta) (20.November.2018)

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Abstract
Dual-rail logic circuits have been used as an effective countermeasure towards a more secure circuit design. However, with technology scaling and lowering of VDD they lose interest as the signal reduction is less significant compared to CMOS. In this work, we revisit dual-rail logic designs (more specifically DDSLL) while focusing on intrinsic physical device noise using a transient noise analysis methodology and show that there exists a potential for such circuits to reduce the signal and concretely increase the noise. Our analysis, which extends to meaningful cryptographic figures-of-merit (FoMs) such as the SNR (Signal-to-Noise ratio) and Mutual-Information (MI), better clarifies the potential of DDSLL circuits to leverage the noise.
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Nawaz, K., Levi, I., Standaert, F.-X., & Flandre, D. (2018). A Transient Noise Analysis of Secured Dual-rail based Logic Style. 2nd New Generation of Circuits & Systems Conference (NGCAS 2018), Valetta (Malta). https://hdl.handle.net/2078.5/227464