Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and Parasitic Elements

Kazemi Esfeh, Babak;Kilchytska, Valeriya;Parvais, Bertrand;Planes, N.;Raskin, Jean-Pierre;et.al.
(2017) 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2017) — Location: Athens (Greece) (3.April.2017)

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This work demonstrates that the back-gate terminal of a 28nm FDSOI MOSFET can be used up to several tens of GHz for signal processing. Furthermore, the dependence of the main RF figures-of-merit on the back gate bias are experimentally extracted using a 3-port characterization in the frequency range of 10 MHz – 26.5 GHz. We propose a small-signal equivalent circuit constructed based on 3-port measurements allowing for more complete extraction of parasitic elements comparing to the 2-ports one. The effect of back-gate bias on cut-off frequencies is demonstrated and explained in terms of its influence on the relevant parasitic elements.
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Kazemi Esfeh, B., Kilchytska, V., Parvais, B., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2017). Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and Parasitic Elements. Proceedings of EUROSOI-ULIS 2017. Published. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2017), Athens (Greece). https://doi.org/10.1109/ULIS.2017.7962569 (Original work published 2017)