Linearity enhancement in asymmetric self-cascode composed by FD SOI nMOSFETs

Assalti, Rafael;de Souza, Michelly;Flandre, Denis
(2018) 2018 33rd Symposium on Microelectronics Technology and devices (SBMicro 2018) — Location: Bento Gonçalves, Rio Grande do Sul, Brazil (27.August.2018)

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Authors
  • Assalti, RafaelDepartment of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil
    Author
  • de Souza, MichellyDepartment of Electrical Engineering, Centro Universitário FEI, São Bernardo do Campo, Brazil
    Author
  • Flandre, DenisUCLouvain
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Abstract
In this paper, the linearity of the Asymmetric Self-Cascode composed by Fully Depleted SOI nMOSFETs is experimentally evaluated, using transistors with different channel lengths. The abnormal (flat) transconductance of this composite transistor is used to promote a linearity enhancement. Disregarding the gain, the minimum harmonic distortion for low-power low-voltage applications has been obtained for the shortest transistor near the source and longest transistor near the drain.
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Assalti, R., de Souza, M., & Flandre, D. (2018). Linearity enhancement in asymmetric self-cascode composed by FD SOI nMOSFETs. Proceedings of SBMicro 2018. Published. 2018 33rd Symposium on Microelectronics Technology and devices (SBMicro 2018), Bento Gonçalves, Rio Grande do Sul, Brazil. https://hdl.handle.net/2078.5/173595 (Original work published 2018)