Low loss Si-substrates enhanced using buried PN junctions for RF applications
(2019) IEEE Electron Device Letters — Vol. 40, n° 5, p. 690-693 (2019)
Files
IEEEElectronDeviceLetters.pdf
Open Access - Adobe PDF
- 841.95 KB
Details
- Authors
- Abstract
- A novel method for increasing the effective resistivity in low-doped silicon substrates is presented. By creating a chain series of p-n depletion junctions beneath the insulator, the parasitic surface conduction channel is interrupted, significantly lowering substrate losses and reducing harmonic distortion in the simulated and measured CPW lines achieving performance close to the widely used trap-rich silicon substrate at RF frequencies.
- Affiliations
Citations
Rack, M., Nyssens, L., & Raskin, J.-P. (2019). Low loss Si-substrates enhanced using buried PN junctions for RF applications. IEEE Electron Device Letters, 40(5), 690-693. https://hdl.handle.net/2078.5/170006 (Original work published 2019)