Substrate-related RF performance of trap-rich High-Resistivity SOI wafers
(2014)
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- Abstract
- HR-SOI technology is currently addressing mobile challenges allowing heterogeneous integration on a single chip for RF, mixed-signal and SoC applications. HR-SOI substrate decreases RF losses and substrate coupling enabling the integration of high performance passive on-chip components. Nevertheless, it is known that a highly conductive inversion/accumulation layer beneath the BOX degrades the high resistivity properties of the handle wafer, thus increases RF losses, non-linearity behavior and coupling through the substrate. Engineered trap-rich HR-SOI substrate is well placed to recover the high resistivity properties of the handle wafer enhancing its RF performance in terms of linearity, reduction of losses and coupling effects. In this thesis, based on wideband electrical measurements the crosstalk of HR-Si substrate with and without a trap-rich layer has been modeled. It has been demonstrated that the quasi-lossless trap-rich (TR) HR-Si substrate can be described by a purely capacitive network. A photo-conductive CPW RF switch structure has been designed and characterized. Thanks to the trapping layer surrounding the active area of the optical RF switches a drastic reduction of the optical crosstalk effect due to the lateral photo-generation in HR-Si substrate is achieved. Static and RF performances of passive and active FD SOI MOSFETs have been characterized on Smart-Cut HR-SOI and TR-SOI (commercially named as Enhanced Signal Integrity, eSI) wafers manufactured by Soitec, France. Small- and large-signal measurements indicate a significant improvement in linearity, reduction of RF losses and crosstalk, as well as much larger Q factor for thick-metal spiral inductors on trap-rich substrate. It has been demonstrated that the introduction of trap-rich layer underneath the BOX does not alter the DC and RF performances of SOI CMOS transistors. Moreover, the digital substrate noise is reduced by more than 25 dB on TR-SOI wafer compared with HR-SOI. Temperature measurements of TR-SOI substrate have shown that intrinsic free carriers thermo-generated inside the HR Si substrate degrade its RF performance above 125 °C. The generation of traps in the Si substrate volume is required to keep a quasi-lossless Si-based substrate at higher temperature. Porous silicon demonstrated its efficiency over a wide temperature range, from 25 °C up to 175 °C. Based on all these experiments and simulations, trap-rich Si-based substrate concept paves the way for more integration of mixed signal, digital, analog and photonic devices on single chip.
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Ben Ali, K. (2014). Substrate-related RF performance of trap-rich High-Resistivity SOI wafers. https://hdl.handle.net/2078.5/48254