45nm PD SOI FET gate resistance optimization for mmw applications
(2018) 2018 IEEE S3S Conference — Location: Burlingame (USA) (15.October.2018)
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- Abstract
- This paper investigates the impact of phosphorous polysilicon gate pre-doping and silicide thickness on the gate resistance of NFETs. The analysis is performed on a 45nm partially depleted (PD) Silicon-on-Insulator (SOI) technology with a Ni silicided poly SiON gate stack. It is shown that both process features contribute differently to Rg improvements, making their respective benefits dependent on device finger width (Wf). The data also show that combining both approaches can simultaneously improve Rg and, consequently, device maximum oscillation frequency (Fmax) on both small and large Wf devices.
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Citations
Lederer, D., Jain, S., Saarop, S., Kumar, A., & Freeman, G. (2018). 45nm PD SOI FET gate resistance optimization for mmw applications. 2018 IEEE S3S Conference, Burlingame (USA). https://hdl.handle.net/2078.5/228715