C-V characterization of the trap-rich layer in a novel Double-BOX structure
(2024) Solid-State Electronics — Vol. 218, p. 108951 (2024)
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- Abstract
- A new Double-BOX structure is introduced to explore the electrical properties of the trap-rich layer used to enhance the performance of radio frequency Silicon-on-Insulator substrates. Capacitance-voltage (C-V) measurements reveal anomalous behavior with a “shoulder” emerging in the electron accumulation region and a shift towards negative gate voltage in hysteresis. TCAD simulation shows that these features are related to trap states at the grain boundary in the trap-rich polycrystalline silicon (polysilicon) layer. These traps form a potential barrier and affect the C-V curves. To determine the traps density in polysilicon, a three-element circuit model is used. The effective density of fast traps is evaluated from the corrected C-V curve, while the hysteresis of double-sweep C-V measurement yields the slow traps density at the grain boundary in polysilicon.
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Citations
Huang, Y., Liu, F., Cristoloveanu, S., Ma, S., Nabet, M., Yan, Y., Li, B., Li, B., Nguyen, B.-Y., Han, Z., & Raskin, J.-P. (2024). C-V characterization of the trap-rich layer in a novel Double-BOX structure. Solid-State Electronics, 218, 108951. https://hdl.handle.net/2078.5/242568 (Original work published 2024)