Self alignment method by buried mask implantation for double gate MOS and nano devices fabrication
(2005) Union Radio-Scientifique Internationale (U.R.S.I.) — Location: Palace of the Academies, Brussels (Belgium) (10.December.2004)
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- Abstract
- The Silicon-on-Insulator (SOI) technology allows the fabrication of devices with reduced parasitic capacitances compared to bulk CMOS yielding higher switching speed . Another advantage of this technology is the resistance to radiations and high temperatures . The device isolation is also easier to achieve. Thus, fully depleted SOI double gate MOS transistors are promising devices. The active layer of double gate transistor being very thin, the inversion layer extends over the whole active silicon film giving rise to volume conduction, which increases drain current and transconductance and decreases the floating body effect . The threshold voltage is better controlled and the short channel effects are reduced. The double gate architecture makes the subthreshold swing nearly ideal.
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Citations
Charavel, R., & Raskin, J.-P. (2005). Self alignment method by buried mask implantation for double gate MOS and nano devices fabrication. Belgian Journal of Electronics and Communications (Revue HF Tijdschrift), 57-58. https://hdl.handle.net/2078.5/228699