RF harmonic distortion modeling in CPW lines on silicon-based substrates including non-equilibrium carrier dynamics
(2017) 2017 IEEE/MTT-S International Microwave Symposium - IMS 2017 — Location: Honololu, HI, USA (4.June.2017)
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- Abstract
- In this paper, a simulation methodology is presented that takes carrier dynamics into account, disallowing instantaneous changes in substrate carrier concentrations, and providing more accurate estimations of harmonic distortion (HD) components. Using this method, we simulated the HD components introduced in a CPW line on various flavors of Si-based substrates. The results are compared to measured HD components over a wide range of bias points and at three fundamental excitation frequencies from 900 MHz to 4 GHz. It is shown that carrier relaxation times are of first importance for understanding the HD levels introduced by Si-substrates at RF frequencies and above. Further-more, characteristic dips in the extracted HD components, for increasing fundamental power, are evaluated and shown to be tightly linked to the position of the device's DC bias voltage relative to the substrate's flatband voltage. The new simulation tool is also capable of capturing these typical dips in the HD curves, and provides physical insight into the reasons behind their existence.
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Citations
Rack, M., & Raskin, J.-P. (2017). RF harmonic distortion modeling in CPW lines on silicon-based substrates including non-equilibrium carrier dynamics. 2017 IEEE MTT-S International Microwave Symposium (IMS). Published. 2017 IEEE/MTT-S International Microwave Symposium - IMS 2017, Honololu, HI, USA. https://doi.org/10.1109/mwsym.2017.8058737