Extrinsic gate capacitance model for UTBB MOSFETs
(2018) Semiconductor Science and Technology — Vol. 33, n° 1, p. 9 pages (2018)
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- Authors
Kazemi Esfeh, Babak 
- Abstract
- Ultra-thin body and buried oxide transistors have gained attention as candidates for near future CMOS technology nodes. Recent studies have pointed out that the total parasitic gate capacitance becomes an important concern for very-high frequency performance. In this paper a semi-analytical model to describe the total extrinsic gate capacitance for ultrathin silicon body and buried oxide transistors is presented. The developed model considers the main technological parameters and has been verified by finite-element numerical simulations as well as by comparison with experimental measurements. The relative weight of the main parasitic components is addressed as well as their impact over the current gain cut-off frequency. Finally, the possibility to improve the cut-off frequency by about 35% due to the reduction of the parasitic gate capacitance is highlighted.
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Citations
Martinez-Lopez A.G., Tinoco J.C., Lezama G., Conde J.E., Kazemi Esfeh, B., & Raskin, J.-P. (2018). Extrinsic gate capacitance model for UTBB MOSFETs. Semiconductor Science and Technology, 33(1), 9 pages. https://hdl.handle.net/2078.5/169995 (Original work published 2018)