Impact of gate to source/drain alignment on the static and RF performance of junctionless Si nanowire n-MOSFETs
(2020) Solid-State Electronics — Vol. 169, p. 107817 (2020)
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- Abstract
- We present experimental results for junctionless nanowire transistors (JNTs) with different gate alignments to the nanowire. Devices with nanowire source/drain extensions (NSDE) show high series source/drain resistance due to the low doped nanowire extensions, which causes lower drive current and larger device performance variations comparing with devices in which the gate electrode overlaps with the source/drain contact pads (GSD). Due to the improved on-current GSD devices exhibit much higher cutoff frequency. The high fringing field in the NSDE JNT results in degradation of SS. An optimized “dumbbell” shape JNT structure is proposed to further improve the device performance. Our preliminary simulations demonstrate higher on-currents but also larger parasitic capacitances for the dumbbell JNT. However, the RF performance of the dumbbell JNT is still improved with a factor similar to our experiments. Much smaller fringing field for the dumbbell JNT is expected from the simulation, which can cause less device variations.
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Citations
Han, Q., Liu, M., Kazemi Esfeh, B., Raskin, J.-P., & Zhao, Q.-T. (2020). Impact of gate to source/drain alignment on the static and RF performance of junctionless Si nanowire n-MOSFETs. Solid-State Electronics, 169, 107817. https://doi.org/10.1016/j.sse.2020.107817. (Original work published 2020)