Traps characterization in RF SOI substrates including a buried SiGe layer
(2025) Solid-State Electronics — Vol. 226, n° 16, p. 109103 (2025)
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- Abstract
- This work analyzes the interface traps density (Dit) at the SiO2/SiGe interface of a buried SiGe stressor SOI substrate, and demonstrates the impact of those traps on the effective resistivity (ρeff) of the substrate. The C-V behavior of MOS capacitors and the RF insertion loss along coplanar waveguide transmission lines on various substrates are measured. TCAD simulations are employed to interpret the traps characteristics and to forecast the RF performance of a buried SiGe stressor SOI wafer having a high resistivity handle Si substrate. The results demonstrate that thanks to the interface traps introduced by the SiGe layer the substrate effective resistivity (ρeff) is enhanced.
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Citations
Yan, Y., & et al. (2025). Traps characterization in RF SOI substrates including a buried SiGe layer. Solid-State Electronics, 226(16), 109103. https://doi.org/10.1016/j.sse.2025.109103 (Original work published 2025)