Substrate noise mitigation using high resistivity base silicon wafer for a 14 GHz VCO on 28 nm FD-SOI
(2024) 2024 19th European Microwave Integrated Circuits Conference (EuMIC) — Location: Paris, France (23.September.2024)
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- Abstract
- This paper studies the impact of substrate resistivity on the sideband spurs generated at the output of a 14 GHz voltage-controlled oscillator (VCO) because of noise signal propagation through the substrate. A VCO has been designed in the 28 nm fully depleted Silicon-on-Insulator (FD-SOI) technology and implemented on a standard (15 Ω.cm), a high resistivity (3 kΩ.cm with parasitic surface conduction) and a trap-rich (3 kΩ.cm without parasitic surface conduction) silicon base wafer. The output spectrum of the VCO (around fosc) when injecting a 10 dBm noise signal at a frequency of 10 MHz (fnoise) into the substrate is simulated, showing spurs generated at fosc ±fnoise , and at other higher-order modulation products. The results obtained on the high resistivity substrate show a reduction of 10 dB of the fosc±fnoise sideband spurs compared to those on the standard resistivity substrate. The spurs are further reduced by more than 90 dB when a trap-rich SOI wafer is used. Those results highlight the important impact of substrate resistivity and parasitic surface conduction on the signal integrity of CMOS VCOs.
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Bendou, Y., Rack, M., Lederer, D., cathelin, A., & Raskin, J.-P. (2024). Substrate noise mitigation using high resistivity base silicon wafer for a 14 GHz VCO on 28 nm FD-SOI. 2024 19th European Microwave Integrated Circuits Conference (EuMIC), 355-358. https://doi.org/10.23919/EuMIC61603.2024.10732151