Low-loss silicon substrates with PN passivation in 28 nm FD-SOI
(2025) Solid-State Electronics — Vol. 229, n° 109174 (2025)
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- Abstract
- In this work, the 28 nm FD-SOI technology from ST Microelectronics was run for the first time on high-resistivity wafer samples. The gain in RF performance through the use of high-resistivity bulk is characterized in terms of losses, effective resistivity (ρeff) and generated harmonics through on-wafer measurements of coplanar waveguides (CPW). Beyond the use of a high-resistivity bulk, special care was taken to ensure a state of high-resistivity at the silicon/oxide interface. This was achieved through the PN junction interface passivation solution, implemented locally on the wafer at the foundry level, below passive RF devices. A study was performed on the dose and energy parameters of these implants to achieve optimal RF performance and giving insight into the PN design.
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Citations
Rack, M., Nabet, M., Bendou, Y., Vanbrabant, M., M.Moulin, Courte, Q., S. Cremer, A.Cathelin, Lederer, D., & Raskin, J.-P. (2025). Low-loss silicon substrates with PN passivation in 28 nm FD-SOI. Solid-State Electronics, 229(109174). https://doi.org/10.1016/j.sse.2025.109174 (Original work published 2025)