Transistor-level design of low-power nanoscale digital circuits for secure applications
(2012)
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- Authors
- Supervisors
- Flandre, Denis
- Abstract
- (en) Highly power-constrained secure applications such as RFIDs, present a great challenge for circuit designers who try to determine the best tradeoff between security and performance. “Computationally” secure applications are not secure anymore due to the physical information leakage of the hardware implementations that use static CMOS (e.g. the power consumption, ... etc.). These types of physical information leakage are exploited by side-channel attacks. Consequently, it is the responsibility of circuit designers to develop new techniques that maximize the security of the implementation with minimum cost in terms of power consumption and area in light of the growing concern of variability associated to nano-CMOS technologies as well. Hardware-level solutions, specially DDL styles are seemingly attractive. Unfortunately, most of the proposed DDL styles in the literature consume and occupy a minimum of 2x the power and area of static CMOS, respectively. The work of this PhD thesis aims at optimizing the design of the previously introduced DDSLL style for low power, small area and adequate security enhancement compared to static CMOS. A DDSLL S-box is implemented on a LP 65 nm CMOS technology and it consumes ~ power to static CMOS and occupies ~ area. Also, DDSLL is 10x harder to attack than static CMOS. Even though the security gain of DDSLL is not sufficient compared to other types of countermeasures, its low power consumption and area overheads give more room to combine countermeasures.
- Affiliations
Citations
Kamel, D. (2012). Transistor-level design of low-power nanoscale digital circuits for secure applications. https://hdl.handle.net/2078.5/159931