Exploiting forward back-biasing capabilities of FDSOI CMOS technology for unified ULP clock generation and PVT compensation
(2022)
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- Authors
- Supervisors
- Bol, David
- Abstract
- Sensitivity to process, voltage, and temperature (PVT) variations constitutes a serious obstacle in ultralow-voltage/ultralow-power (ULV/ULP) circuits and systems. In this thesis, we address this challenge in the domains of clock generation and frequency synthesis by exploiting the forward back-biasing (FBB) feature of 28-nm FDSOI CMOS technology. We tackle three questions: - How do FDSOI-enabled back-bias-controlled oscillators (BBCOs) compare to conventional current-starved ring oscillators (CSROs)? - How to leverage FBB in BBCO-based phase-locked loops (PLLs)? - How to exploit FBB in adaptive regulation loops for unified clock generation and PVT compensation in ULV/ULP circuits? We first show that BBCOs can intrinsically reach lower power and slightly better power/noise compromises compared to CSROs. We then identify several design challenges linked to the practical use of BBCOs in feedback loops and illustrate how to tackle them by proposing three silicon prototypes. Embedded within a 2.5 Gb/s ultra-wideband radio, our first demonstrator is a BBCO-based dual-PLL clock recovery unit. Thanks to FBB, it reaches a competitive energy level and an excellent power/jitter trade-off. Our last two prototypes are custom ULV/ULP microcontroller units (MCUs) which benefit from a unified frequency and back-bias regulation scheme. This new adaptive technique has limited power/area overheads while providing many advantages at the MCU level: PVT compensation, robustness against voltage droops, fast transitions between active and sleep modes, and energy efficiency.
- Affiliations
Citations
Schramme, M. (2022). Exploiting forward back-biasing capabilities of FDSOI CMOS technology for unified ULP clock generation and PVT compensation. https://hdl.handle.net/2078.5/104359