Unified 1/f noise SOI MOSFET modelling for circuit simulation
(1997) Electronics Letters — Vol. 33, n° 21, p. 1781-1782 (1997)
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- Abstract
- The authors address the modelling of 1/f noise in SOI MOS devices for circuit simulation. A simple and unified model is presented which is valid for all operating regimes; it is verified by comparison with noise measurements. It is shown that this model is especially useful for low-power SOI MOS circuit design.
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Citations
Iniguez, B., Tambani, M., Dessard, V., & Flandre, D. (1997). Unified 1/f noise SOI MOSFET modelling for circuit simulation. Electronics Letters, 33(21), 1781-1782. https://doi.org/10.1049/el:19971196 (Original work published 1997)