Low leakage SOICMOS static memory cell with ultra-low power diode
(2007) IEEE Journal of Solid State Circuits — Vol. 42, n° 3, p. 689-702 (2007)
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- Abstract
- A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode. The biasing of MOS transistors in very weak inversion, with negative gate-to-source voltages, results in a static current that lies orders of magnitude below that of conventional cross-coupled CMOS inverters. Based on our device, a 7-transistors SRAM cell is presented. Modeling, simulation and experimental characterization of the main properties of this cell are reported for a 0.13 mu m Partially-Depleted SOI CMOS process. The feasibility of ultra-low leakage memory circuits is demonstrated experimentally by the design of a 256 x 1 bits SRAM column.
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Citations
Levacq, D., Dessard, V., & Flandre, D. (2007). Low leakage SOICMOS static memory cell with ultra-low power diode. IEEE Journal of Solid State Circuits, 42(3), 689-702. https://doi.org/10.1109/JSSC.2006.891494 (Original work published 2007)