Measurement and modeling of thin-film accumulation-mode SOI p-MOSFET intrinsic gate capacitances
(1996) Solid-State Electronics — Vol. 39, n° 7, p. 1071-1078 (1996)
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- Abstract
- Small-signal a.c. measurements of accumulation-mode SOI p-MOSFET intrinsic gate capacitances have been performed and interpreted in relation to the device physics. A first-order analytical model has been developed which successfully predicts the main features of the capacitance behavior, such as a unique two-step dependence on the front gate voltage or a kink in the transition between the triode and saturation regime. The influence of the surface- and the buried-channel conduction mode on this behavior is clearly established. Validation of the model is obtained by a fair agreement between calculated and measured capacitances in all regimes of operation. The model can be straightforwardly extended to n-channel accumulation-mode transistors. This work proposes the first basic steps towards a general charge-based simulation model for SOI CMOS digital and analog circuits. Copyright (C) 1996 Elsevier Science Ltd.
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Citations
Gentinne, B., Flandre, D., & Colinge, J.-P. (1996). Measurement and modeling of thin-film accumulation-mode SOI p-MOSFET intrinsic gate capacitances. Solid-State Electronics, 39(7), 1071-1078. https://doi.org/10.1016/0038-1101(95)00408-4 (Original work published 1996)