Recent advances in SOI MOSFET devices and circuits for ultra-low power / high temperature applications

Levacq, David;Dessard, Vincent;Flandre, Denis
(2004) Proceedings of the NATO Advanced Research Workshop on Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment — ISBN: [1-4020-3011-8], p. 133-144, published

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Authors
  • Levacq, DavidUCLouvain
    Author
  • Dessard, VincentCISSOID, Louvain-la-Neuve, Belgium
    Author
  • Flandre, DenisUCLouvain
    Author
Abstract
This work focuses on new structures with ultra-low power dissipation. They are based on a new diode architecture that features ultra-low leakage current and a negative impedance in its reverse bias mode. This characteristic allows to realize an ultra-low power (ULP) latch with strongly reduced static current at stable states. We propose to implement this latch in new MTCMOS flip-flops where the supply voltage can be gated by high threshold voltage transistors to reduce the static power dissipation in the sleep mode. The presence of the ULP latch avoids data loss during standby. The work is supported by simulations in 0.12µm PD CMOS/SOI.
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Levacq, D., Dessard, V., & Flandre, D. (2004). Recent advances in SOI MOSFET devices and circuits for ultra-low power / high temperature applications. In D. Flandre, A.N. Nazarov, P.L.F. Hemment (ed.), Proceedings of the NATO Advanced Research Workshop on Science and Technology of Semiconductor-On-Insulator Structures and Devices Operating in a Harsh Environment (p. p. 133-144). Kluwer Academic Publishers. https://doi.org/10.1007/1-4020-3013-4_14