Acore-CIM: build accurate and robust mixed-signal CIM cores with RISC-V controlled self-calibration
(2026) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems — p. 1 (2026)
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Acore-CIM_build_accurate_and_robust_mixed-signal_CIM_cores_with_RISC-V_controlled_self-calibration.pdf
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- Authors
Numan, Omar 
Adam, Kazybek Leslin, Jelin Andraud, Martin
- Abstract
- The development of accurate and robust compute-in-memory (CIM) architectures is a central research focus for accelerating artificial intelligence (AI) tasks, particularly deep neural networks (DNNs). Significant interest has emerged in ana-log and mixed-signal CIM architectures to improve the efficiency of data storage and computation, as well as to manage the large data volumes required by DNNs. Recent advances in emerging non-volatile memory (eNVM) solutions have driven progress in resistive mixed-signal CIM cores. However, mixed-signal CIM computing cores continue to face integration and robustness challenges that limit their widespread adoption in end-to-end AI computing systems. From an integration perspective, resistive and eNVM-based CIM cores require integration with a control processor to enable programmable acceleration. Additionally, SRAM-based CIM architectures remain more efficient and easier to program than eNVM-based alternatives. In terms of robust-ness, analog circuits are more susceptible to variations, leading to computation errors and reduced accuracy. This study addresses both challenges by introducing a self-calibrated mixed-signal CIM accelerator system-on-chip (Acore-CIM), fabricated using 22-nm FD-SOI technology. Integration is achieved through (1) a CIM architecture that combines the density and programmability of SRAM-based weight storage with multi-bit computation using linear resistors, alongside (2) an open-source programming and testing strategy for CIM systems. Accuracy and robustness are enhanced through automated RISC-V-controlled on-chip calibration, which improves compute signal-to-noise ratio (SNR) by 25-45 % across columns (reaching 18-24 dB) and reduces process-induced multiply-and-accumulate (MAC) error spread by up to 82 %. To demonstrate scalability, the proof-of-concept system-on-chip (SoC) is shown to be extendable to recent high-density linear resistor technologies, further enhancing computing performance. Index Terms-AI accelerator, computing-in-memory (CIM), deep neural network (DNN), self-calibration, RISC-V.
- Affiliations
Citations
Numan, O., Singh, G., Adam, K., Leslin, J., Korsman, A., Simola, O., Kosunen, M., Ryynänen, J., & Andraud, M. (2026). Acore-CIM: build accurate and robust mixed-signal CIM cores with RISC-V controlled self-calibration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1. https://doi.org/10.1109/tcad.2026.3682622 (Original work published 2026)