Integration of large passive components on silicon for high-voltage galvanic isolation
(2026)
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- (en) The continuous increase in switching frequencies and power densities in modern power electronic systems necessitates the use of galvanically isolated gate drivers to ensure user safety and protect low-voltage control circuitry from high-voltage transients, particularly in high-side configurations operating at floating potentials. Galvanic isolation devices—based on optocouplers, capacitive coupling, or magnetic transformers are widely employed to enable safe power and signal transfer by preventing hazardous current flowbetween voltage domains while maintaining reliable communication and control. However, commercial digital isolators exhibit several limitations. They typically occupy large areas, are implemented on FR4 substrates, and are generally incapable of transferring more than approximately 0.55 W to the high-voltage side. This power level is insufficient for supplying the integrated microelectronic circuits and sensors required to control modern wide-bandgap devices such as GaN and SiC transistors. Integrating galvanic isolation devices directly onto silicon substrates therefore represents a promising approach to reduce system size, enhance performance, and increase transferable power. In addition, such approach enables monolithic integration with the gate driver circuitry, thereby reducing the overall footprint, minimizing signal propagation delay, and mitigating parasitic inductances and capacitances associated with long wire bonds. Nevertheless, this approach remains highly challenging. High power transfer requires thick metal layers capable of sustaining large current densities, while robust galvanic isolation demands thick dielectric layers with high breakdown strength. Reconciling these conflicting requirements within standard silicon microfabrication processes, while maintaining simple and cost-effective fabrication without additional postprocessing steps, constitutes a major technological challenge. This thesis addresses these limitations through the design, fabrication, and characterization of an integrated galvanic isolation device based on on chip transformers. The proposed device is capable of delivering more than 1 W of power while employing a thick dielectric layer (>26 𝜇m) designed to withstand surge voltages up to 10 kV and maintain a coupling capacitance below 2 pF at 200 MHz. The work is structured around three main research axes. First, the impact of the silicon substrate on large-area passive devices is investigated through measurements and simulations. The results demonstrate that high-resistivity silicon incorporating a trap-rich layer significantly enhances performance, increasing the inductor quality factor by more than 2.5×, capacitor performance by over 5×, and transformer efficiency by a factor of two, without requiring additional post-processing steps. Second, a hybrid dielectric stack is developed, combining thick low-stress (70 MPa) polyimide HD4110 layers (>24 𝜇m) with thin inorganic barrier layers (Al2O3–SiO2–Si3N4). This structure reduces leakage current by a factor of five compared to a standalone polyimide layer, while maintaining a low dielectric constant (3.2) to minimize coupling capacitance. The low residual stress also mitigates mechanical failure in thick dielectric films. Third, a hybrid transformer architecture is proposed, featuring a nonspiral inductor as the bottom primary winding and a spiral inductor as the top secondary winding. This configuration reduces losses, simplifies fabrication, and enhances efficiency, enabling power transfer exceeding 1 W. Furthermore, the lateral offset between the two inductors reduces coupling capacitance. Finally, the integrated device occupies an area of 25 mm2 and operates at 200 MHz, a frequency selected to reduce signal propagation delay. The transformer successfully delivers more than 1Wof power to a 200 Ω load, demonstrating robust performance under demanding conditions. The proposed fabrication approach, which avoids complex post-processing steps, is validated by achieving accurate alignment between windings despite the presence of a thick dielectric layer.
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Zeidi, N. (2026). Integration of large passive components on silicon for high-voltage galvanic isolation. https://hdl.handle.net/2078.5/275977