SOI technology for single-chip harsh environment microsystems

Flandre, Denis;Laconte, Jean;Levacq, David;Afzalian, Aryan;Raskin, Jean-Pierre;et.al.
(2004) Conference on Micro-Nano-Technologies for Aerospace Applications (CANEUS 2004) — Location: Monterey (USA) (1.November.2004)

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Abstract
Silicon-on-Insulator (SOI) technology is emerging as a major contender for heterogeneous microsystems applications. It is indeed well known that SOI CMOS integrated circuits yield quasi-ideal properties for micropower and RF functionalities, as well as for high-temperature operation up to e.g. 350DGC. In addition SOI substrates offer unique opportunities for implementing sensors and MEMS. Such devices and circuits can further be combined to co-integrate high-performance intelligent/smart micro-systems on a single SOI substrate. The present talk will report recent SOI developments of thin-film Si sensors (temperature, magnetic, UV) and thin dielectric membranes (flow, gas, pressure) as well ultra-low-power/high-temperature CMOS circuits, of potential interest for aerospace applications (e.g. structural or environmental monitoring). Future possibilities of multi-SOI substrates will also be discussed.
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Flandre, D., Laconte, J., Levacq, D., Afzalian, A., Rue, B., Renaux, C., Iker, F., Olbrechts, B., André, N., & Raskin, J.-P. (2004). SOI technology for single-chip harsh environment microsystems. Proceedings of the Conference on Micro-Nano-Technologies for Aerospace Applications (CANEUS 2004), 157-169. https://hdl.handle.net/2078.5/272253