Vialess non-spiral on-chip stacked transformer on high-resistivity silicon for improved RF power transfer efficiency
(2025) Microelectronic Engineering — Vol. 302, p. 112424 (2026)
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- Abstract
- On-chip transformers are fundamental components in integrated circuits, serving key functions such as impedance matching, signal coupling, voltage conversion, and galvanic isolation in high-frequency and mixed-signal systems. However, their performance is often limited by factors like substrate losses, interwinding capacitance, and series resistance, which reduce both bandwidth and efficiency. This paper presents a novel non-spiral, vialess stacked on-chip transformer featuring a compact 620 μm × 620 μm footprint, utilizing only two metal layers to achieve enhanced high-frequency power transfer efficiency. Key performance metrics, such as quality factor (Q), coupling coefficient (Kim), self-resonant frequency, and maximum power transfer efficiency, are compared against those of interleaved and interwinding transformers, all under identical geometric constraints, using both experimental measurements and electromagnetic simulations. All devices were fabricated on a high-resistivity silicon substrate with a trap-rich layer (HR-Si + TR), providing a quasi-insulated platform that significantly reduces substrate losses. Despite the interwinding transformer achieving the highest coupling coefficient (Kim = 0.96) and the interleaved transformer showing superior Q-factors (Q1 = Q2 = 5.7), the proposed non-spiral stacked design demonstrates the larger peak power transfer efficiency of 0.72 at 2.5 GHz, outperforming the interleaved (0.60 at 2.66 GHz) and interwinding (0.45 at 0.90 GHz) configurations. Moreover, the design maintains this performance superiority even on standard low-resistivity silicon, confirming its robustness and suitability for passive RF integration in CMOS-compatible processes. This efficiency enhancement stems from an exceptionally low mutual resistive coupling, achieved through strong vertical magnetic linkage and reduced series resistance in parallel conductor paths.
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Zeidi, N., Tounsi, F., Raskin, J.-P., & Flandre, D. (2025). Vialess non-spiral on-chip stacked transformer on high-resistivity silicon for improved RF power transfer efficiency. Microelectronic Engineering, 302, 112424. https://doi.org/10.1016/j.mee.2025.112424 (Original work published 2026)