A High-Speed Stateful Packet Processing Approach for Tbps Programmable Switches
(2023) 20th USENIX Symposium on Networked Systems Design and Implementation (NSDI 23) — Location: New York (24.April.2023)
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- Abstract
- High-speed ASIC switches hold great promise for offloading complex packet processing pipelines directly in the highspeed data-plane. Yet, a large variety of today’s packet processing pipelines, including stateful network functions and packet schedulers, require storing some (or all the) packets for short amount of times in a programmatic manner. Such a programmable buffer feature is missing on today’s high-speed ASIC switches. In this work, we present RIBOSOME, a system that extends programmable switches with external memory (to store packets) and external general-purpose packet processing devices such as CPUs or FPGAs (to perform stateful operations). As today’s packet processing devices are bottlenecked by their network interface speeds, RIBOSOME carefully transmits only the relevant bits to these devices. RIBOSOME leverages spare bandwidth from any directly connected servers to store the incoming payloads through RDMA. Our evaluation shows that RIBOSOME can process 300G of traffic through a stateful packet processing pipeline (e.g., firewall, load balancer, packet scheduler) by running the pipeline logic on a single server equipped with one 100G interface.
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Citations
Mariano Scazzariello, Tommaso Caiazzi, Hamid Ghasemirahni, Barbette, T., Dejan Kostic, & Marco Chiesa. (2023). A High-Speed Stateful Packet Processing Approach for Tbps Programmable Switches. Proceedings of the 20th USENIX Symposium on Networked Systems Design and Implementation (NSDI 23). Published. 20th USENIX Symposium on Networked Systems Design and Implementation (NSDI 23), New York. https://hdl.handle.net/2078.5/256364 (Original work published 2023)