Supporting Time-Based QoS Requirements in Software Transactional Memory

Maldonado, Walther;Marlier, Patrick;Felber, Pascal;Lawall, Julia;Riviere, Etienne;et.al.
(2015) A C M Transactions on Parallel Computing — Vol. 2, n° 2, p. 1-30 (2015)

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Authors
  • Maldonado, WaltherUniversity of Neuchâtel, Switzerland
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  • Marlier, PatrickUniversity of Neuchâtel, Switzerland
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  • Felber, PascalUniversity of Neuchâtel, Switzerland
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  • Lawall, JuliaInria/LIP6/UPMC/Sorbonne University, France
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Abstract
Software transactional memory (STM) is an optimistic concurrency control mechanism that simplifies parallel programming. However, there has been little interest in its applicability to reactive applications in which there is a required response time for certain operations. We propose supporting such applications by allowing programmers to associate time with atomic blocks in the form of deadlines and quality-of-service (QoS) requirements. Based on statistics of past executions, we adjust the execution mode of transactions by decreasing the level of optimism as the deadline approaches. In the presence of concurrent deadlines, we propose different conflict resolution policies. Execution mode switching mechanisms allow the meeting of multiple deadlines in a consistent manner, with potential QoS degradations being split fairly among several threads as contention increases, and avoiding starvation. Our implementation consists of extensions to an STM runtime that allow gathering statistics and switching execution modes. We also propose novel contention managers adapted to transactional workloads subject to deadlines. The experimental evaluation shows that our approaches significantly improve the likelihood of a transaction meeting its deadline and QoS requirement, even in cases where progress is hampered by conflicts and other concurrent transactions with deadlines.
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Citations

Maldonado, W., Marlier, P., Felber, P., Lawall, J., Muller, G., & Riviere, E. (2015). Supporting Time-Based QoS Requirements in Software Transactional Memory. A C M Transactions on Parallel Computing, 2(2), 1-30. https://doi.org/10.1145/2779621 (Original work published 2015)