Analog Implementation of a Kohonen Map With On-chip Learning
(1993) IEEE Transactions on Neural Networks — Vol. 4, n° 3, p. 456-461 (1993)
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- Authors
Legat, Jean-Didier 
- Abstract
- Kohonen maps are self-organizing neural networks that classify and quantify n-dimensional data into a one- or two-dimensional array of neurons [1]-[2]. Most applications of Kohonen maps use simulations on conventional computers, eventually coupled to hardware accelerators or dedicated neural computers. The small number of different operations involved in the combined learning and classification process makes however the Kohonen model particularly suited to a dedicated VLSI implementation, taking full advantage of the parallelism and speed that can be obtained on the chip. We propose here a fully analog implementation of a one-dimensional Kohonen map, with on-chip learning and refreshment of on-chip analog synaptic weights. The small number of transistors in each cell allows a high degree of parallelism in the operations, what greatly improves the computation speed compared to other implementations. This paper will emphasize on the storage of analog synaptic weights, based on the principle of current copiers; it will be shown that this technique can be used successfully for the realization of VLSI Kohonen maps.
- Affiliations
Citations
Macq, D., Jespers, P., Legat, J.-D., & Verleysen, M. (1993). Analog Implementation of a Kohonen Map With On-chip Learning. IEEE Transactions on Neural Networks, 4(3), 456-461. https://doi.org/10.1109/72.217188 (Original work published 1993)