Design of Complementary Low-Power CMOS Architectures for Looser-take-all and Winner-take-all.

Dualibe, Carlos;Verleysen, Michel;Donckers, Nicolas
(1999) 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems (MicroNeuro′99) — Location: Granada (Spain) (7.April.1999)

Files

45-Designofcomplementarylow-powerCMOSarchitecturesforLooser-Take-AllandWinner-Take-All.pdf
  • Restricted Access
  • Adobe PDF
  • 74.1 KB
Request a copy

Details

Authors
  • Dualibe, CarlosUniversidad Católica de Córdoba
    Author
  • Verleysen, MichelUCLouvain
    Author
  • Donckers, NicolasUCLouvain
    Author
Abstract
A novel architecture for winner-take-all (WTA) and looser-take-all (LTA) circuits is proposed. As compared with other realisations, the LTA does not require input subtraction from a reference, which decreases accuracy and input dynamics. The architectures have been designed using the gm/ID methodology. As it will be shown, this method allows a rapid new dimensioning when specifications are modified. Both the WTA and the LTA can operate with low voltage supply, and show better speed characteristics (delay and raising time) for a 6 bits accuracy and a typical consumption of 50 μW/cell than previous realisations.
Affiliations

Citations

  • APA
  • Chicago
  • FWB

Dualibe, C., Verleysen, M., & Donckers, N. (1999). Design of Complementary Low-Power CMOS Architectures for Looser-take-all and Winner-take-all. Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems (MicroNeuro′99), p. 360-365. https://hdl.handle.net/2078.5/253826