Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations

Van Brandt, Léopold;Bonnin, Michèle;Banaszeski da Sila, Mauricio;Bolcato, Pascal;Flandre, Denis;et.al.
(2025) IEEE Transactions on Circuits and Systems Part 1: Regular Papers — Vol. 72, n° 34, p. 989-1002 (2025)

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Stability of ultra-low-voltage SRAM bitcells in retention mode is threatened by two types of uncertainty: process variability and intrinsic noise. While variability dominates the failure probability, noise-induced bit flips in weakened bitcells lead to dynamic instability. We study both effects jointly in a unified SPICE simulation framework. Starting from a synthetic representation of process variations introduced in a previous work, we identify the cases of poor noise immunity that require thorough noise analyses. Relying on a rigorous and systematic methodology, we simulate them in the time domain so as to emulate a true data retention operation. Short times to failure, unacceptable for a practical ultra-low-power memory system application, are recorded. The transient bit-flip mechanism is analyzed and a dynamic failure criterion involving the unstable steady state is established. We conclude that, beyond static variability, the dynamic noise inflates defectiveness among SRAM bitcells. Then, a stochastic nonlinear model, fully characterizable from conventional deterministic SPICE simulations, is presented. We then leverage it to efficiently and accurately predict the mean time to failure with an analytical Eyring-Kramers formula, recently extended to account for the varying-noise behavior of nonlinear systems.
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Van Brandt, L., Bonnin, M., Banaszeski da Sila, M., Bolcato, P., Wirth, G. I., & Flandre, D. (2025). Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations. IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 72(34), 989-1002. https://doi.org/10.1109/TCSI.2024.3525387 (Original work published 2025)