Efficient Single Event Upset Simulations of a Tolerant PD SOI CMOS D Flip-Flop
(2009) 10th European Conference on Radiation Effects on Components and Systems (RADECS′09) — Location: Bruges (Belgium) (14.September.2009)
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- Authors
- Abstract
- A simple way for modeling the single event upset (SEU) in Partially Depleted (PD) SOI CMOS circuits by Spice simulations is presented. A Verilog-A module connected to the body contact of PD SOI MOSFET is implemented to describe the transient current generated by an ion-track crossing the transistor. Verilog-A module is given by a physical based compact model and hence accounts for all variations in MOSFET's physical parameters (i.e. mobility, lifetime, etc.) caused by irradiation, temperature, bias conditions, etc. Good agreement with mixed-mode numerical simulations is observed at different conditions. Both kinds of simulations show that PD SOI CMOS D Flip-Flop is tolerant to high LET energies, whereas bias supply reduction as well as an increase in the clock frequency of the flip-flop can degrade this tolerance.
- Affiliations
Centre de Recherches du Cyclotron
Citations
Alvarado Pulido, J. J., Kilchytska, V., Berger, G., & Flandre, D. (2009). Efficient Single Event Upset Simulations of a Tolerant PD SOI CMOS D Flip-Flop. Proceedings of RADECS′09, 10th European Conference on Radiation Effects on Components and Systems, 225-229. https://hdl.handle.net/2078.5/253446