RF SOI CMOS Technology on 1st and 2nd Generation Trap-Rich High Resistivity SOI Wafers

Kazemi Esfeh, Babak;Kilchytska, Valeriya;Flandre, Denis;Raskin, Jean-Pierre
(2016) 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS 2016) — Location: Vienne (Austria) (25.January.2016)

Files

RFSOICMOSTechnologyon1stand2ndGenerationTrap-RichHighResistivitySOIWafers.pdf
  • Restricted Access
  • Adobe PDF
  • 806.9 KB
Request a copy

Details

Authors
Abstract
In this work 3 different types of UNIBOND Silicon-on-Insulator 5SOI) wafers including one standard and two types of trap-rich high-resistivity HR-SOI substrates provided by SOITEC are studied. The DC and RF performances of these wafers are compared by means of passive and active devices, coplanar waveguide (CPW) lines and partially-depleted (PD) SOI MOSFETs respectively.
Affiliations

Citations

  • APA
  • Chicago
  • FWB

Kazemi Esfeh, B., Kilchytska, V., Flandre, D., & Raskin, J.-P. (2016). RF SOI CMOS Technology on 1st and 2nd Generation Trap-Rich High Resistivity SOI Wafers. Proceedings de la conférence EUROSOI-ULIS 2016, 159-161. https://doi.org/10.1109/ULIS.2016.7440077