Using OCTO SOI nMOSFET to Reduce Die Area of Analog Integrated Circuits
(2012) VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012 — Location: Sao Bernardo do Campo (Brazil) (12.April.2012)
Files
No attached file found for this publication.
Details
- Authors
- Affiliations
Citations
Fino, L., Renaux, C., Gimenez, S., & Flandre, D. (2012). Using OCTO SOI nMOSFET to Reduce Die Area of Analog Integrated Circuits. Proceedings of the VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012. Published. VII Workshop on Semiconductor and Micro & Nano Technology, SEMINATEC 2012, Sao Bernardo do Campo (Brazil). https://hdl.handle.net/2078.5/253379