Sub-45 nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications

Bol, David;Legat, Jean-Didier;Ambroise, Renaud;Flandre, Denis
(2008) 2008 IEEE International SOI Conference — Location: New Paltz, NY, USA (6.October.2008)

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The improved immunity of FD SOI technology against short-channel effects has been shown to offer a great interest for subthreshold logic in terms of delay and energy per operation at medium throughputs (108 Op/s). Moreover, the combination of an undoped channel with a metal gate extends this benefit to lower throughputs by a reduction of the minimum functional V/sub dd/ and static energy. This makes FD SOI with metal gate a strong candidate for sub-45 nm robust and energy-efficient subthreshold circuits.
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Bol, D., Legat, J.-D., Ambroise, R., & Flandre, D. (2008). Sub-45 nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications. Proceedings of the 2008 IEEE International SOI Conference, 57-58. https://doi.org/10.1109/SOI.2008.4656292