Experimental evidence for reduction of gate tunneling current in FinFET structures and its dependence on the Fin width
(2006) 36th European Solid-State Device Research Conference (ESSDERC 2006) — Location: Montreux (Suisse) (19.September.2006)
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- Authors
- Abstract
- In this work, we present for the first time experimental evidence for the reduced gate tunneling current density in narrow FinFET structures compared to quasi-planar very wide-fin structures. This reduction is observed for both nand p-channel and is found to be larger for HfO2 than for SiON. For a given gate dielectric, the above reduction depends on the fin width. For SiON with an equivalent oxide thickness of 1.8 nm in undoped n-channel devices, it varies from factor of 2.1 to 5.2, when the fin width decreases from 80 to 20 nm
- Affiliations
Lashkaryov Institute of Semiconductor Physics (ISP), Kyiv IMEC Ukraine National Academy of Science Institute of Semiconductor Physics
Citations
Rudenko, T., Kilchytska, V., Collaert, N., Jurczak, M., Nazarov, A., & Flandre, D. (2006). Experimental evidence for reduction of gate tunneling current in FinFET structures and its dependence on the Fin width. Proceedings of the 36th European Solid-State Device Research Conference (ESSDERC 2006), 375-378. https://hdl.handle.net/2078.5/253355