A circuit level 65nm node bulkand SOI technologies comparison for analog amplifiers

Pollissard, Guillaume;Flandre, Denis
(2011) Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011) — Location: Granada (Espagne) (17.January.2011)

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This work aims at demonstrating the effectiveness of advanced SOI CMOS technologies from an analog circuit designer point of view. After a quick review of the compared analog figures of merit of bulk SOI technologies of the same 65nm node, we will present an automated sizing tool developed to target given specifications and deduce the remaining degrees of freedom. With this tool, we can fairly compare the SOI and bulk designs of a test amplifier.
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Pollissard, G., & Flandre, D. (2011). A circuit level 65nm node bulkand SOI technologies comparison for analog amplifiers. Proceedings of the Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011). Seventh Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EUROSOI 2011), Granada (Espagne). https://hdl.handle.net/2078.5/253340