Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology
(1997) IEEE Journal of Solid State Circuits — Vol. 32, n° 7, p. 1006-1012 (1997)
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- Abstract
- A systematic study of the gain-boosted regulated-cascode operational transconductance amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behaviour and second to propose design criteria for optimal settling time. A synthesis procedure based on the “gm/ID” methodology is considered further on for quick optimization of the architecture based on the dc open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed.
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Flandre, D., Viviani, A., Eggermont, J.-P., Gentinne, B., & Jespers, P. (1997). Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. IEEE Journal of Solid State Circuits, 32(7), 1006-1012. https://doi.org/10.1109/4.597291 (Original work published 1997)