On the UTBB SOI MOSFET Performance Improvement in Quasi-Double-Gate Regime
(2012) 2012 European Solid-State Device Research Conference (ESSDERC 2012) — Location: Bordeaux (France) (17.September.2012)
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- Abstract
- This work investigates the simultaneous electrostatic improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing gate and substrate (or ground plane) as Vsub=k*Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. QDG mode is demonstrated to allow threshold voltage tuning and on-current enhancement without off-state current degradation, of interest for digital applications (e.g. switches). Improved performance in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. The work finally quantifies the resulting gate area decrease in QDG mode, potentially exploitable in actual circuit implementations.
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Citations
Kilchytska, V., Andrieu, F., & Flandre, D. (2012). On the UTBB SOI MOSFET Performance Improvement in Quasi-Double-Gate Regime. Proceedings of the 2012 European Solid-State Device Research Conference (ESSDERC 2012), 246-249. https://doi.org/10.1109/ESSDERC.2012.6343379