Quasi-Double Gate Mode for Sleep Transistors in UTBB FD SOI Low-Power High-Speed Applications

Bol, David;Kilchytska, Valeriya;De Vos, Julien;Andrieu, François;Flandre, Denis
(2012) 2012 IEEE International SOI Conference — Location: Napa (USA) (1.October.2012)

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Abstract
Power-gating enables low stand-by power for high-speed applications. In this paper, we exploit the unique feature of quasi-double gate (QDG) mode MOSFETs in UTBB SOI to boost the performances of the power-gating sleep transistor. According to experimental results on a 10-nm BOX, at nominal Vg QDG mode enables up to 35% width and thereby leakage reduction for the sleep transistor. At circuit level, a charge pump architecture is proposed to generate the QDG back-gate bias for a 100-mA power-gated CPU with sub-100 ns wake-up/sleep times and negligible power/area overheads.
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Bol, D., Kilchytska, V., De Vos, J., Andrieu, F., & Flandre, D. (2012). Quasi-Double Gate Mode for Sleep Transistors in UTBB FD SOI Low-Power High-Speed Applications. Proceedings of the 2012 IEEE International SOI Conference, 2. https://doi.org/10.1109/SOI.2012.6404370