A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode

Bol, David;Schramme, Maxime;Moreau, Ludovic;Haine, Thomas;Flandre, Denis;et.al.
(2019) 2019 IEEE International Solid- State Circuits Conference - (ISSCC) — Location: San Francisco (USA) (17.February.2019)

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A40-to-80MHzSub-4μW-MHzULVCortex-M0MCUSoCin28nmFDSOIwithDual-LoopAdaptiveBack-BiasGeneratorfor20μsWake-UpFro.pdf
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Authors
  • Bol, Davidorcid-logoUCLouvain
    Author
  • Schramme, MaximeUCLouvain
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  • Moreau, LudovicUCLouvain
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  • Haine, ThomasUCLouvain
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  • Xu, PengchengUCLouvain
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  • Frenkel, CharlotteUCLouvain
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  • Dekimpe, Rémiorcid-logoUCLouvain
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  • Flandre, DenisUCLouvain
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Abstract
Near-threshold circuits operating at ultra-low voltage (ULV) have matured with integration in commercial products such as ultra-low-power (ULP) MCUs for the IoT [1]. In this market, MCU design faces the key performance tradeoff between speed, active power, deep-sleep retention power and wakeup time, with the challenge of preserving it over PVT corners. We present a ULP MCU SoC in 28nm FDSOI codenamed SleepRunner, exploiting back biasing (BB) capability of FDSOI to push the performance tradeoff beyond the state of the art.
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Bol, D., Schramme, M., Moreau, L., Haine, T., Xu, P., Frenkel, C., Dekimpe, R., Stas, F., & Flandre, D. (2019). A 40-to-80MHz Sub-4µW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI with Dual-Loop Adaptive Back-Bias Generator for 20µs Wake-Up From Deep Fully Retentive Sleep Mode. Proceedings of the 2019 IEEE International Solid- State Circuits Conference (ISSCC 2019), 322-323. https://doi.org/10.1109/ISSCC.2019.8662293