Impact of the Graded-Channel Architecture on Double Gate Transistors for High-Performance Analog Applications

Pavanello, Marcelo Antonio;Martino, Joao Antonio;Chung, Tsung Ming;Kranti, Abhinav;Flandre, Denis;et.al.
(2003) 11th International Symposium Silicon-on-Insulator Technology and Devices, Electrochemical Society Meeting — Location: Paris (France) (27.April.2003)

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  • Pavanello, Marcelo AntonioCentro Universitario da FEI
    Author
  • Martino, Joao AntonioCentro Universitario da FEI
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  • Chung, Tsung MingUCLouvain
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  • Kranti, AbhinavUCLouvain
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  • Raskin, Jean-PierreUCLouvain
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  • Flandre, DenisUCLouvain
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Abstract
This work introduces the use of Gate-All-Around SOI MOSFETs using the Graded-Channel (GC) architecture for analog circuits and compare their performance with both conventional and GC single-gate (SG) fully depleted (FD) SOI transistors. It is demonstrated that Graded-Channel GAA MOSFETs can provide extremely improved Early voltage and high transconductance and drive current in comparison to the conventional GAA and SG FD MOSFETs with similar dimensions.
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Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J.-P., & Flandre, D. (2003). Impact of the Graded-Channel Architecture on Double Gate Transistors for High-Performance Analog Applications. In S. Cristoloveanu (ed.), Proceedings of the 11th International Symposium Silicon-on-Insulator Technology and Devices (pp. 261-266). https://hdl.handle.net/2078.5/253250