Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications

Kranti, Abhinav;Chung, Tsung Ming;Flandre, Denis;Raskin, Jean-Pierre
(2003) 33rd European Solid-State Device Research Conference (ESSDERC 2003) — Location: Estoril (Portugal) (16.September.2003)

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Based on analytical modeling, 2D simulation and experimental results, this work demonstrates the potential benefits of using laterally asymmetric channel design over uniform doping in DG SOI MOSFETs for achieving excellent analog performance. We show that the asymmetric channel design in DG MOSFETs makes it possible to achieve a DC gain of 80 dB, an Early voltage of over 1200 V and nearly ideal values (/spl sim/38 V/sup -1/) of transconductance-to-current ratio for L/sub eff/ = 1.64 /spl mu/m, well in excess of those reported so far. Analysis shows new opportunities for realising future high performance analog circuits with GC DG MOSFETs.
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Kranti, A., Chung, T. M., Flandre, D., & Raskin, J.-P. (2003). Analysis of laterally asymmetric channel design in fully depleted double gate (DG) SOI MOSFETs for high performance analog applications. Proceedings of the 33rd European Solid-State Device Research Conference (ESSDERC 2003), 131-134. https://doi.org/10.1109/ESSDERC.2003.1256828