Linearity Analysis in Double Gate Graded-Channel SOI Devices Applied to 2-MOS MOSFET-C Balanced Structures
(2008) 23rd Symposium on Microelectronics Technology and Devices (SBMicro 2008) — Location: Gramado (Brazil) (1.September.2008)
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- Authors
- Abstract
- This paper examines the linearity of 2-MOS MOSFET-C balanced structures using conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices. The distortion analysis has been performed through the evaluation of third order harmonic distortion (HD3). The study has been carried out through experimental results, two-dimensional process and device simulations. Along this work, the best operation bias in terms of HD3 is determined for each analysed device and the couple device that exhibits lower HD3 is pointed out. The use of GC GAA devices in 2-MOS structures has showed to improve the linearity in relation to the conventional GAA. Finally, a discussion over the non-linearities causes is performed clarifying their origins and the improvement provided by the adoption of GC GAA devices in 2-MOS structures.
- Affiliations
University of Sao Paulo CINVESTAV Department of Electrical Engineering Centro Universitário da FEI, São Bernardo do Campo, SP, Brazil Department of Electrical Engineering
Citations
Doria, R. T., Cerdeira, A., Raskin, J.-P., Flandre, D., & Pavanello, M. A. (2008). Linearity Analysis in Double Gate Graded-Channel SOI Devices Applied to 2-MOS MOSFET-C Balanced Structures. Proceedings of SBMICRO 2008, the 23rd Symposium on Microelectronics Technology and Devices, 273-282. https://hdl.handle.net/2078.5/253226