Disruptive ultra-low-leakage design techniques for ultra-low-power CMOS circuits
(2012) CMOS Emerging Technologies Conference — Location: Vancouver (Canada) (18.July.2012)
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- Abstract
- We introduce a disruptive ultra-low-leakage design technique, based on a pair of source-connected n- and p-MOSFETs, auto-biasing the stand-by gate-to-source voltage of the nMOSFET at negative voltage and that of the p-device at positive, thereby pushing the off current of analog and digital functions towards its physical limits, without reducing functional performance. Therefrom, we designed ultra-low-power basic blocks (2-terminal diode, 3-terminal transistor, voltage follower), circuits (7-transistor SRAM and MTCMOS latch with record low leakage but still high speed), as well as microsystems (e.g. high-frequency power-management units for RF and PV energy harvesting and micro<att interface for implanted capacitive sensors).
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Citations
Flandre, D., Bulteel, O., Gosset, G., Haddad, P.-A., Bernard, S., Rue, B., & Bol, D. (2012). Disruptive ultra-low-leakage design techniques for ultra-low-power CMOS circuits. Proceedings of the CMOS Emerging Technologies Conference. Published. CMOS Emerging Technologies Conference, Vancouver (Canada). https://hdl.handle.net/2078.5/253181