Operation of double gate graded-channel transistors at low temperatures
(2003) Seventh International Symposium on Low Temperature Electronics - as a part of the 204th Meeting of The Electrochemical Society — Location: Orlando (USA) (12.October.2003)
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- Abstract
- This work studies the use of graded-channel profile on double gate SOI MOSFETs from room temperature down to 95 K with the aim of studying the analog performance. Two-dimensional simulations are performed to provide a physical explanation for the improved analog device characteristics given by the double gate graded-channel MOSFETs. It is demonstrated that double gate graded-channel MOSFETs can provide extremely improved Early voltage, high transconductance and drive current in comparison to the conventional double gate fully depleted SOI MOSFETs with similar dimensions. A degradation in the Early voltage as the temperature decreases has been found but this reduction reflects negligibly in the low frequency open loop gain for a temperature range of 150 K to 300 K due compensation provided by the transconductance to drain current ratio.
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Pavanello, M. A., Martino, J. A., Chung, T. M., Kranti, A., Raskin, J.-P., & Flandre, D. (2003). Operation of double gate graded-channel transistors at low temperatures. Proceedings of the Seventh International Symposium on Low Temperature Electronics, 50-60. https://hdl.handle.net/2078.5/253180